-by Giles Peckham & Adam Taylor
Automotive electrical systems have experienced rapid technological growth thanks to Moore’s law. Modern automobiles have evolved from simple engine electrical systems, coupled with an AM radio. Today’s modern vehicles contain several advanced electronic systems, performing such functions as engine control, Advanced Driver Assistance Systems (ADAS), traction and stability control to infotainment, and in some cutting-edge applications, the ability for autonomous operation.
This significant increase in the deployment of electronic systems within automobiles brings with it several challenges which must be addressed by the designers:
- Performance – Real time, low latency and highly deterministic performance is required to implement many vehicle features such as ADAS, ECU, Traction and Stability Control.
- Security – Automotive electronic systems implement critical functionality where malfunction could result in injury or loss of life. Systems must therefore implement information assurance and anti-tamper techniques to prevent unauthorised modifications.
- Safety – Must conform within the Automotive Safety Integrity Levels as defined by ISO26262.
- Interfacing – Must be able to interface with a wide range of sensors, drives and other actuators.
- Power Efficiency – Must operate efficiently within a constrained power budget.
- Software Defined – Enabling flexibility to address the differing standards and conditions in a range of markets.
To address these challenges, developers of automotive electronic systems are deploying heterogeneous System on Chip (SoC) devices. Heterogeneous devices combinea processing unit, usually multi-core, with one or multiple heterogeneous co-processors for example GPU, DSP or Programmable Logic.
Combining a processing unit with programmable logic forms a tightly integrated system, enabling the inherent parallel nature of the programmable logic to be leveraged. Thisallows the programmable logic (PL) to be used to implement high performance algorithms and interfacing,while the processing system implements higher-level decision making, communication and system management functions. When combined, this enables the creation of a more responsive, deterministicand power efficient solution thanks to the ability to offload processing into the programmable logic.
When it comes to interfacing, the heterogeneous SoC cansupport a range of industry-standard interfaces which can be implemented via the processing system or the programmable logic. Crucially legacy and bespoke interfaces can be implemented using the programmable logic thanks to the flexibility of the IO structures. This does however, require the addition of an external PHY to achieve the physical layer of the protocol providing any-to-any connectivity.
Someheterogeneous SoCsfacilitate several device-level and system-level security aspects which can be implemented with ease. These devices provide the ability to encrypt and authenticate the boot and configuration process. If the processor core is based upon ARM processors, then Trustzonecan be used to secure the software environment. With Trustzone, the development team can create orthogonal worlds limiting software access to the underlying hardware, with the use of a hypervisor. There are also several additional design choices, such as functional isolation, which can be implemented in the design to further strengthen the security solution dependent upon the requirements.
The traditional development flow of a heterogeneous SoC segments the design between the processor system and the programmable logic. Such an approach has in the past required two separate development teams, which increased the non-recurring engineering cost, development time and technical risk. This approach also fixed design functions as being in the processor cores or the programmable logic, making later optimisations difficult.
What was required was a development tool which enables software defined development of the entire device, with the ability to move functions from processor cores to programmable logic as required, without the need to be an HDL Specialist.
This is where a System Optimising Compiler is used.A System Optimising Compiler enables software definition of the entire system behaviourusing high-level languages such as C, C++ or OpenCL. Functional partitioning between processor system and the programmable logic is then performed using the system optimising compiler, which has the capacity to seamlessly move functions between running in the processor system or being implemented in the programmable logic.
Identification of which functions are causing bottlenecks can be performed using inbuilt timers within the processing system to time the execution of functions, creating a list of bottleneck functions. These bottleneck functions are then candidates for acceleration into the programmable logic using the System Optimising Compiler.
This movement between the processing system and programmable logic is enabled by the System Optimising Compiler’s combination of High Level Synthesis, a tool which can convert C, C++, OpenCL into a Verilog or VHDL description, and a software defined connectivity framework. The software-defined connectivity frameworkseamlessly connects the results of the HLS into the software application, enabling the design team to move functions between the processor and the programmable logic with the click of a button. Of course, when users move functionality to the programmable logic they also gain a significant performance increase which comes naturally with the use of the programmable logic. Acceleration into the PL also provides an increase in determinism and a lower latency compared to a CPU / GPU solution which is very important for applications such as ECU and ADAS.
Many automotive applications are developed using industry standard open source libraries, for example the use of OpenCV or Caffe in ADAS systems or standard maths libraries within an ECU. To enable faster development for these applications,a system optimising compiler needs to be able to support several HLS libraries which the developers can use in their applications. There are several key libraries which a System Optimising Compiler should support,these include:
- OpenCV – Ability to accelerate computer vision functions
- Caffe– Ability to accelerate machine learning inference engines
- Math Library – Provides synthesisable implementations of the standard math libraries.
- IP Library – Provides IP libraries for implementing FFT, FIR, and Shift Register LUT functions.
- Linear Algebra Library – Provides a library of commonly used linear algebra functions.
- Arbitrary Precision Data Types Library – Provides support for non-power-of-2, arbitrary length data using signed and unsigned integers. This library allows developers to use the FPGA’s resources more efficiently.
Supplying these librariesprovides the development team with a considerable boost as they do not need to develop similar functions.
Real World Example
One key element of many automotive applications is securing data to prevent unauthorised modifications, which may result in unsafe operation. One common algorithm used to secure both stored and transmitted data is Advanced Encryption Standard (AES). AES is a good example of an algorithm which is described at a high level, but best implemented in programmable logic fabric. To demonstrate the benefit of using a System Optimising Compiler,a simple AES 256 application targeted at three commonly used operating systems was developed. This example was first executed only in the processor system and then with functions accelerated into the programmable logic.
Heterogeneous SOCsare able to address the challenges faced by automotive electronic system designers. System Optimising Compliers enable the development of these devices using a high-level language, with the functional partitioning between the processor system and the programmable logic able to be optimized once the application functionality has been developed and prototyped using the processor, thus reducing the development time and producing a more secure, responsive and power-efficient solution.